1. Field of the Invention
The present invention is directed to a system for interfacing two asynchronous machines by using a single-port RAM synchronized with the master clock of only one of the machines. The invention also relates to devices to implement such a system.
2. Description of the Related Art
The simplest way known to interface asynchronous equipment, i.e. two machines each operating with independent master clock signals (CKsource, CKchannel, with frequencies FCKsource and FCKchannel, respectively) is to utilize a dual-port RAM, to which the clock signals of the two systems direct 14 access. This conventional system is shown in FIG. 1 where, for purposes of clarity, the two asynchronous machines are not represented, but instead are indicated by the signals they exchange with a dual-port RAM 2. However, this type of memory (dual-port RAM) has at least two significant disadvantages:
(i) Higher access time as compared to a single-port RAM. The maximum operating frequency of dual-port RAM's is on the order of 10 MHz. This is insufficient, for example, for video applications (with frequencies ranging from 15 MHz and higher).
(ii) Costs and consumption are considerably higher as compared to single-port RAM's. This disadvantage becomes particularly critical when large memory dimensions are required. In fact, at present, only a small quantity of dual-port RAM's are available on the market.